Controlling The Fmc230; Architecture - 4DSP FMC230 User Manual

UM023 FMC230 User Manual
22mA @ 12V
Total Power
Consumption:
+/- 5.6W
1010mA @ VADJ*
1010mA @ 3.3V**
* VADJ may be used when 2.5V
to save power consumption.
** 3.3V is the factory default
assembly to cover most FMC
carrier hardware.
169 mA @ 12V
Power plane
VADJ
3P3V
12P0V
3P3VAUX (Operating)
3P3VAUX (Standby)
Table 5: Typical / Maximum current drawn from FMC carrier card

5 Controlling the FMC230

5.1 Architecture

The data interface of one DAC channel occupies 31 differential pairs on the FMC connector.
Since one DAC channel is available on the LPC connections, there are only six signals left on
the LPC connections to control the board. Therefore, the FMC will be controlled from a single
SPI interface connecting to an onboard CPLD (Xilinx Coolrunner-II XC2C64A-QFG). Four
connections are available between the FMC connector and the CPLD. The CPLD acts as a
SPI distribution device and level translator and comes factory programmed. The two remaining
signals on the FMC connector are reserved.
UM023
ADP2301
ADP7182
45mW
48mW
(Eff. 85%)
ADP151
263mW
ADP1753
990mW
ADP151
263mW
Selected by
assembly
ADP2301
406mW
(Eff. 85%)
Figure 7: Power supply tree
www.4dsp.com
120mA @ -1.5V
Max. 200mA
660mA @ 1.8V
Max. 800mA
ADP151
8mW
ADP1753
135mW
Max. 800mA
Typical Maximum
0.2A + I
VIO_B
1.0A
0.2A
0.1 mA
0.01 µA
r1.11
330mA @ 1.8Vd
AD9129
175mA @ 1.8Va
850mW
60mA @ -1.5Va
330mA @ 1.8Vd
AD9129
175mA @ 1.8Va
850mW
60mA @ -1.5Va
TCXO
25mA @ 3.3V
TX3-801
AD9517
455mA @ 3.3V
1.5W
-
1.1A
0.3A
3 mA
1 µA
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