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UM023 FMC230 User Manual
DAC0_P0_P<13..0>
DAC0_P0_N<13..0>
DAC0_P1_P<13..0>
DAC0_P1_N<13..0>
DAC1_DCO_P
DAC1_DCO_N
DAC1_SYNC
DAC1_DCI_P
DAC1_DCI_N
DAC1_FRM_P
DAC1_FRM_N
DAC1_P0_P<13..0>
DAC1_P0_N<13..0>
DAC1_P1_P<13..0>
DAC1_P1_N<13..0>
CLK_TO_FPGA_P
CLK_TO_FPGA_N
EXT_TRIGGER_P
EXT_TRIGGER_N
FMC_TO_CPLD<3..0>
CLK_DIR
PG_C2M
PG_M2C
I2C_SCL
I2C_SDA
UM023
D/A 0
Input
D/A 0
Input
D/A 1
Output
D/A 1
Output
D/A 1
Input
D/A 1
Input
D/A 1
Input
D/A 1
Input
I/O
Output
I/O
Output
CONTROL
Bidir
CONTROL
Output
STATUS
Input
STATUS
Output
I2C
Input
I2C
Bidir
Table 8: FMC230 Signal Description
www.4dsp.com
LVDS
Data bus 0 going to the 1st D/A converter.
LVDS
Data bus 1 going to the 1st D/A converter.
LVDS
Clock coming from the 2nd D/A converter.
Sync output, when enabled this output is
1.8V
DACCLK/8. Only available on r1.2 boards
CMOS
or later
LVDS
Clock going to the 2nd D/A converter.
LVDS
Frame going to the 2nd D/A converter.
LVDS
Data bus 0 going to the 2nd D/A converter.
LVDS
Data bus 1 going to the 2nd D/A converter.
Clock coming from the clock tree. Typically
LVDS
used for debug and monitoring purposes.
Representation of the external trigger
LVDS
signal.
SPI bus to CPLD on the FMC176:
FMC_TO_CPLD(0): SPI Clock
CMOS
FMC_TO_CPLD(1): SPI Chip Select (low active)
VIO
FMC_TO_CPLD(2): SPI Data In/Out
FMC_TO_CPLD(3): SPI Alert/Interrupt
CLK_DIR is not connected. CLK2 and
LVTTL
CLK3 are unused.
Power good indicator from carrier to
LVTTL
module.
Power good indicator from module to
LVTTL
carrier.
LVTTL
I2C clock line.
LVTTL
I2C data line.
-
r1.11
- 22
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