Pll Design - 4DSP FMC230 User Manual

UM023 FMC230 User Manual
Ref
Clock
The AD9517 has four LVPECL outputs. OUT2 and OUT3 are used for clocking the DAC
devices. The other four clock outputs can be programmed either as LVDS or LVCMOS33.
These outputs have the ability to enable a programmable delay. OUT4 is connected to the
FMC connector for test and monitoring purposes. OUT5 connects to the gigabit transceiver
reference clock on the FMC connector (as a build option it can be connected to OUT7). OUT6
connects to the clock output on a MMCX connector.

4.9.1 PLL design

The PLL functionality of the AD9517 is used to operate from an internal sampling clock to
enable flexibility in frequency selection while maintaining high performance.
The default loop filter is designed for a phase detector frequency of 7.68MHz (f
bandwidth of 10KHz, phase margin of 45 deg, and a charge pump of 4.8mA.
Lower phase detector frequencies might be required to achieve the required output clock
frequency (phase detector frequency equals the VCO tuning step size). Whether the loop filter
design still works for other configurations should be investigated case by case.
UM023
TCXO
REF_EN
30.72MHz
Figure 5: Clock tree
www.4dsp.com
Loop
Filter
r1.11
DAC 0
DAC 1
To FMC
To GBT
To OUT
/4), loop
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