On-Chip System Buses And Bus Bridges - Infineon Technologies TC1796 User Manual

6

On-Chip System Buses and Bus Bridges

The TC1796 has four independent on-chip buses
• Program Local Memory Bus (PLMB)
• Data Local Memory Bus (DLMB)
• System Peripheral Bus (SPB)
• Remote Peripheral Bus (RPB)
Program Memory
Interface
PMI
48 KB SPRAM
16 KB ICACHE
PBCU
EBU
To Emulation Memory
(Emulation device only )
LDRAM = Local Data RAM
DPRAM = Dual-Port RAM
SPRAM = Scratch-Pad RAM
ICACHE = Instruction Cache
SBRAM = Stand-by RAM
SRAM = Data RAM
PFLASH = Program Memory Flash
DFLASH = Data Memory Flash
BROM = Boot ROM & Test ROM
Figure 6-1 Buses in TC1796 Processor Subsystem
The two LMBs (PLMB and DLMB) connect the TriCore CPU to its local resources for
instruction fetches and data accesses.
User's Manual
Buses, V2.0
Floating Point Unit
CPU Slave Interface
Program Local
Memory Bus
PLMB
Program Memory
Unit
PMU
16 KB BROM
2 MB PFLASH
128 KB DFLASH
Emulation Memory
Interface
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
FPU
TriCore
CPU
CPS
Data Local
Memory Bus
DLMB
Local Memory -to-
FPI Bus Interface
LFI-Bridge
System
Peripheral Bus
SPB
EBU = External Bus Unit
LMI = Local Memory Interface
PBCU = Program Local Memory
Bus Control Unit
DBCU = Data Local Memory
Bus Control Unit
6-1
Data Memory
Interface
DMI
56 KB LDRAM
8 KB DPRAM
DBCU
Data Memory
Unit
LMI
DMU
16 KB SBRAM
64 KB SRAM
MCB05626_mod
V2.0, 2007-07
TC1796