Tc1796 Cpu Subsystem Registers - Infineon Technologies TC1796 User Manual

2.4

TC1796 CPU Subsystem Registers

This section only describes the implementation-specific features of the registers listed in
Table 2-1. For complete descriptions of all registers, please refer to the TriCore 1
Architecture Manual.
TC1796 implementation-specific CPU registers are referred directly in this section.
Table 2-1 CPU and Processor Subsystem Registers
Registers
Core Special
Function Registers
(CSFRs)
CPU Slave Interface
Registers (CPSs)
Core General
Purpose Registers
(GPRs)
Core Debug
Registers (OCDS)
Memory Protection
Registers
Program Memory
Interface Registers
(PMI)
Data Memory
Interface Registers
(DMI)
The complete and detailed address map of the CPU and processor subsystem registers
shown in Table 2-1
Map" of Table 2-1
User's Manual
CPU, V2.0
Purpose
Program state information,
context and stack management,
interrupt and trap control,
system control
Software break control and
software service request control
Address and data
Debug control
Memory protection control and
mode selection
PMI instruction cache control and
status
DMI status and trap flags
above is located in
directly point to the corresponding pages.
System Units (Vol. 1 of 2)
Description
Architecture
Manual
see
Page 2-26
see
Page 2-34
Chapter 18. The entries in column "Address
2-9
TC1796
CPU Subsystem
Address Map
see
Page 18-108
see
Page 18-104
see
Page 18-105
see
Page 18-108
see
Page 18-105
see
Page 18-124
see
Page 18-123
V2.0, 2007-07