Ic Information; Block Diagram - Pioneer DRM-ULV16 Service Manual

1

7.3 IC INFORMATION

• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
LSI53C180-192BGA-K (CONV UNIT: IC901)
A
• SCSI Expander IC
Pin Arrangement (Top view)
A1 A2 A3
VDD
NC NC
IO
B1 B2 B3
B_SD11+ B_SD11- NC
C1 C2 C3
B_SD10+ B_SD10- B_DIFFSENS
D1 D2 D3
B_SD9+ B_SD9- NC
E1 E2 E3
B
VDD
B_SD8+ B_SD8-
SCSI
F1 F2 F3
B_SIO+ B_SIO- NC
G1 G2 G3
B_SREQ+ B_SREQ- VSS
H1 H2 H3
B_SCD- B_SSEL+ B_SCD+
J1 J2 J3
VDD
B_SSEL- B_SMSG+
SCSI
K1 K2 K3
VDD
B_SMSG- B_SRST+
CORE
L1 L2 L3
B_SRST- NC VSS
M1 M2 M3
C
B_SACK+ B_SACK- B_SBSY+
N1 N2 N3
VDD
B_SBSY- B_SATN+
SCSI
P1 P2 P3
B_SATN- B_SDP0- B_SDP0+
R1 R2 R3
B_RBIAS B_SD7+ B_SD7-
T1 T2 T3
NC B_SD6+ B_SD5+
U1 U2 U3
NC B_SD6- B_SD5-
D

Block diagram

Control
Signals
LVD, Single-ended,
Wide Ultra SCSI Bus
(A Side)
E
A_DIFFSENS
F
24
1
2
A4 A5 A6 A7 A8
NC NC XFER_ACTIVE RESET/ A_DIFFSENS
B4 B5 B6 B7 B8
VDD
NC WS_ENABLE/ BSY_LED NC
CORE
C4 C5 C6 C7 C8
VDD
NC NC VSS CLOCK
SCSI
G7 G8
VSS VSS
H7 H8
VSS VSS
J7 J8
VSS VSS
K7 K8
VSS VSS
L7 L8
VSS VSS
R4 R5 R6 R7 R8
NC VDD B_SD2+ VSS B_SD0-
SCSI
T4 T5 T6 T7 T8
B_SD4+ B_SD3+ B_SD2- B_SD1+ B_SD0+
U4 U5 U6 U7 U8
VDD
B_SD4- B_SD3- NC B_SD1-
CORE
Retiming
Logic
Precision State
Delay Machine
Control Control
40 MHz Clock Input
DRM-ULV16
2
3
A9 A10 A11 A12 A13
A_SD12- A_SD13- A_SD14+ A_SD15+ A_SD0-
B9 B10 B11 B12 B13
A_SD12+ A_SD14- A_SD15- A_SDP1- A_SD0+
C9 C10 C11 C12 C13
VDD VDD
A_SD13+ VSS A_SDP1+
SCSI SCSI
G9 G10 G11
VSS VSS VSS
H9 H10 H11
VSS VSS VSS
J10 J11
VSS VSS
K9 K10 K11
VSS VSS VSS
L9 L10 L11
VSS VSS VSS
R9 R10 R11 R12 R13
VDD NC VSS NC VDD
SCSI SCSI
T9 T10 T11 T12 T13
B_SDP1+ B_SD15+ B_SD14+ B_SD13+ B_SD12+
U9 U10 U11 U12 U13
B_SDP1- B_SD15- B_SD14- B_SD13- B_SD12-
LVD, Single-ended
Wide Ultra SCSI Bus
(B Side)
A Side
LVD or SE
SCSI Interface
B_DIFFSENS
Control Signals
3
4
A14 A15 A16 A17
A_SD1- A_SD2- A_SD3- NC
B14 B15 B16 B17
A_SD1+ A_SD2+ A_SD3+ A_SD4-
C14 C15 C16 C17
NC NC A_SD5- A_SD4+
D15 D16 D17
A_SD5+ A_SD6+ A_SD6-
E15 E16 E17
VDD
A_SD7+ A_SD7-
SCSI
F15 F16 F17
NC A_SDP0+ A_SDP0-
G15 G16 G17
VSS A_SATN+ A_SATN-
H15 H16 H17
NC A_SBSY+ A_SBSY-
J15 J16 J17
VDD A_SACK+ A_SACK-
K15 K16 K17
VDD
A_SRST- A_RBIAS
CORE
L15 L16 L17
VSS A_SMSG- A_SRST+
M15 M16 M17
A_SSEL+ A_SSEL- A_SMSG+
N15 N16 N17
VDD
A_SCD+ A_SCD-
SCSI
P15 P16 P17
NC A_SREQ+ A_SREQ-
R14 R15 R16 R17
A_SD10+ A_SD9- A_SIO+ A_SIO-
T14 T15 T16 T17
A_SD11+ A_SD10- A_SD8+ A_SD8-
U14 U15 U16 U17
A_SD11- A_SD9+ NC NC
A_SSEL+ B_SSEL+
A_SSEL- B_SSEL-
A_SBSY+ B_SBSY+
A_SBSY- B_SBSY-
A_SRST+ B_SRST+
A_SRST- B_SRST-
A_SREQ+ B_SREQ+
A_SREQ- B_SREQ-
A_SACK+ B_SACK+
A_SACK- B_SACK-
A_SMSG+ B_SMSG+
A_SMSG- B_SMSG-
A_SCD+ B_SCD+
A_SCD- B_SCD-
SCSI Interface
A_SIO+ LSI53C180 B_SIO+
A_SIO- B_SIO-
A_SATN+ B_SATN+
A_SATN- B_SATN-
A_SDP[1:0]+ B_SDP[1:0]+
A_SDP[1:0]- B_SDP[1:0]-
A_SD[15:0]+ B_SD[15:0]+
A_SD[15:0]- B_SD[15:0]-
A_DIFFSENS B_DIFFSENS
A_RBIAS B_RBIAS
RESET/
WS_ENABLE
BSY_LED
XFER_ACTIVE
CLOCK
4
B Side
LVD or SE