4DSP FMC204 User Manual page 9

UM008 FMC204 User Manual
LVDS Clock
LVDS Trigger
LVDS Sync
DAC #1
LVDS Clock
LVDS Sync
LVDS Data
DAC #2
LVDS Clock
LVDS Sync
LVDS Data
2.5V or VADJ Level I/O
routed to CPLD (see board
revision)
1
Signal CLK3_BIDIR_P/N is not connected.
UM008
# Pairs
1
1
1
1
1
16
1
0
16
# Total pairs
Table 3: HPC signal usage
www.4dsp.com
# Clock pairs # Data pairs
1
1
1
0
3
1
r1.14
18
17
4
39
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