Control; Multi-Gigabit Transceivers - 4DSP FMC204 User Manual

UM008 FMC204 User Manual
RF
Clock
Switch
CLKSRC_SEL0

4.7.1 Control

The clock tree contains two RF switches (ADG918) and requires the following control signals
(driven from the CPLD):

CLKSRC_SEL0 connects the external clock input to the reference input of the
AD9517 or the 2

CLKSRC_SEL1 connect either the onboard VCXO or the external clock to the clock
input of the AD9510. This signal also controls the VCXO power supply

CLKSRC_SEL2 enables/disables the onboard reference oscillator.

4.8 Multi-Gigabit Transceivers

Optionally, the FMC connector hosts 10 MGT pairs (10 Tx and 10 Rx pairs). These are
connected to two 38-pins MICTOR headers. The arrangement is such that different
interconnect topologies are supported;
2
The VCXO should be powered down to avoid interference with the external clock when external
clock is used.
UM008
VC(X)O
Π-attn
1.0 GHz
XTAL
CLKSRC_SEL2
100MHz
RF
Switch
CLKSRC_SEL1
Figure 4: Clock tree
nd
RF switch.
www.4dsp.com
Loop
Filter
r1.14
DAC 1
DAC 0
To FMC
2
.
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