4DSP FMC204 User Manual page 24

FMC204 User Manual
Table 9: HPC signal description (FMC204)
Signal
CLK_TO_FPGA_N D/A 0, D/A 1
CLK_TO_FPGA_P
DAC0_DCLK_N
DAC0_DCLK_P
DAC0_DATA_N<15..0>
DAC0_DATA_P<15..0>
DAC1_DCLK_N
DAC1_DCLK_P
DAC1_DATA_N<15..0>
DAC1_DATA_P<15..0>
DAC_SYNC_N D/A 0, D/A 1
DAC_SYNC_P
TRIGGER_TO_FPGA_N
TRIGGER_TO_FPGA_P
FMC_TO_CPLD<0>
FMC_TO_CPLD<1>
FMC_TO_CPLD<2>
FMC_TO_CPLD<3>
FRONT_IO<3..0>
I2C_SCL
I2C_SDA
Group Direction
Output
D/A 0 Input
D/A 0 Input
D/A 1 Input
D/A 1 Input
Input
TRIGGER Output
CONTROL Input
CONTROL Input
CONTROL Bidir
CONTROL Output
I/O Bidir
CONTROL Input
CONTROL Bidir
r1.13
I/O Standard Description
LVDS Clock to be used as reference clock for generating DAC
clock and data signals. Typically, half of the sample clock
frequency.
LVDS Digital data clock to 1
LVDS Data bus to 1
DAC0_DCLK_P/N (DDR)
LVDS Digital data clock to 2
nd
LVDS Data bus to 2
DAC0_DCLK_P/N (DDR)
LVDS Signal used as transmit enable for both DACs.
LVDS Representation of the signal connected to the external
trigger input.
CMOS VIO SPI clock connected to the CPLD
CMOS VIO SPI chip select connected to the CPLD
CMOS VIO SPI data in/out connected to the CPLD
CMOS VIO Interrupt connected the CPLD (reserved for future use)
CMOS VIO Connected to the transceivers on the HDMI connector
(Table 2). The direction of the transceivers is controlled
through a CPLD register.
LVTTL 3.3V I2C data, connects to the voltage monitoring and EERROM.
LVTTL 3.3V I2C data, connects to the voltage monitoring and EERROM.
st
DAC.
st
DAC. Data should be valid on both edges of
nd
DAC.
DAC. Data should be valid on both edges of