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UM008 FMC204 User Manual
1. Sample clock input, connecting to the clock input of the AD9517.
2. Reference clock input, connecting to the reference input of the AD9517.
4.6 External trigger/sync input
The external trigger input can be configured in different ways with custom build options. The
trigger input can be 50Ω terminated to accept most common high-speed signalling standards
like single-ended LVPECL. By default, the 50Ω termination is not mounted to support
LVTTL/LVCMOS and similar input standards. Differential input is also possible using the
coax shield as inverted signal. By default, the input is single-ended and DC-coupled with an
input impedance of approximately 2.5kΩ. The input threshold is approximately 1.25V.
The trigger input can also be used as sync input, synchronizing local A/D converters or
multiple FMC204 cards.
TRIGGER
Analog Out
Analog Out
Synchronization of multiple D/A devices in parallel is done through the SYNC input. The
SYNC signal is driven by the FPGA and can be derived from the trigger input. Since the
SYNC input has an internal 100R termination resistor, a 1:2 fan-out buffer is used to connect
a single LVDS signal to both D/A converters.
4.7 Clock Tree
The FMC204 offers a clock architecture that combines flexibility and high performance.
Components have been chosen to minimize jitter and phase noise to reduce degradation of
the data conversion performance. The user may use an external or internal sampling clock.
The clock tree has a PLL and clock distribution section. The PLL ensures locking of the
internal clock to an externally supplied reference. There is an onboard reference which is
used if no external reference is present.
A VCO (998-1001MHz, Z-Communications, CLV1000A-LF) is used as internal clock source
and can connect to the distribution section instead of the external clock input. The distribution
section drives the D/A devices with the LVPECL outputs. One LVDS clock output is
connected to the FMC connector as a reference for the digital data transferred to the D/A
devices.
UM008
LVDS
SYNC
DAC #1
SYNC
RESET
SYNCOUT
DAC #2
Figure 3: D/A Synchronization topology
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