Spi Programming - 4DSP FMC204 User Manual

UM008 FMC204 User Manual
Local Side
DAC0_N_CS
DAC1_N_CS
CLK_N_CS
SCLK
SDIO
CLKSRC_SEL[0:2]
SYNCSRC_SEL[0:1]
CLK_N_RESET
DAC_N_RESET
FRONT_IO_DIR[0:3]
FAN_N_EN[0:3]
REFMON
LD
STATUS
VM_N_INT
LED
Notes:

SDO on the AD9517 and DAC5682Z devices is not connected. SDIO is used
bidirectional (3-wire SPI)

N_PD on the AD9517 is not connected.

N_SYNC on the AD9517 on the revision 1 boards is not connected. On revision 2
boards N_SYNC is connected to the CPLD for future use.

N_RESET on the both DAC5682Z devices is shared.

5.2 SPI Programming

The SPI programmable devices on the FMC204 can be accessed as described in their
datasheet, but each SPI communication cycle needs to be preceded with a preselection byte.
The preselection byte is used by the CPLD to forward the SPI command to the right
destination. The preselection bytes are defined as follows:
- CPLD
- DAC5682Z #1
- DAC5682Z #2
- AD9517
The CLPD has three internal registers which are described in Appendix B CPLD Register
map. The registers of the other devices are transparently mapped.
UM008
CPLD
Shift register
SRC_SEL
REG0
REG1
REG2
Figure 8: CPLD architecture
0x00
0x82
0x83
0x84
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Ctrl
AND
r1.14
FMC Side
FMC_TO_CPLD(0)
SCLK
FMC_TO_CPLD(1)
N_CS
FMC_TO_CPLD(2)
SDIO
FMC_TO_CPLD(3)
N_INT
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