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UM008 FMC204 User Manual
Appendix B CPLD Register map
Bit nr.
Bit 7
'0'
Name
Table 10: Register CPLD_REG0 definition
Field
CLKSRC
'000'
'011'
'110'
others
SYNCSRC
'00'
'01'
'10'
'11'
CLKR
'0'
'1'
DACR
'0'
'1'
Table 11: Register CPLD_REG0 description
Bit nr.
Bit 7
Name
FAN3
Table 12: Register CPLD_REG1 definition
UM008
Bit 6
Bit 5
DACR
CLKR
Selection of clock source
External clock
Internal clock, External Reference
Internal clock, Internal Reference
Do not use
Selection of synchronisation source
External Trigger
Carrier (trough SYNC_FROM_FPGA_P/N)
Clock Tree
No Sync
Clock tree SPI reset
Normal operation
Reset, resetting the clock tree is normally not required. This bit is not self-
clearing.
D/A device SPI reset
Normal operation
Reset, resetting the D/A device is normally not required. This bit is not self-
clearing.
Bit 6
Bit 5
FAN2
FAN1
www.4dsp.com
Bit 4
Bit 3
SYNCSRC
Description
Bit 4
Bit 3
FAN0
DIR3
Bit 2
Bit 1
CLKSRC
Bit 2
Bit 1
DIR2
DIR1
r1.14
Bit 0
Bit 0
DIR0
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