Port Allocations - Icom IC-7200 Service Manual

3-6 PORT ALLOCATIONS

• CPU (LOGIC UNIT: IC1)
PIN LINE
No. NAME
1 DTFS DSP data frame (TX)
2 DCK DSP data clock
3 DRXS DSP data (RX)
4 DTXS DSP data (TX)
5 DRESL DSP reset
External bass width setting
6 BYTE
16 bit=H, 8 bit=L, single chip=VSS
8 UPWS USB HUB power supply control
9 UMDS USB modulation input line control
10 RESET Reset signal
16 EBUSY CI-V buss busy input
17 VBUS USB VBUS detect
18 PWRK [PWR] key input
19 BL2S LCD back light DIMMER control
20 BL1S LCD back light DIMMER control
21 USCK USB HUB control (Clock)
22 USDA USB HUB control (Data)
23 RSB [M-CH/RIT] dial phase B input (10 pulse/20 click)
24 RSA [M-CH/RIT] dial phase A input (10 pulse/20 click)
25 MSA [DIAL] phase A input
26 MSB [DIAL] phase B input
27 TKEY Key signal for optional tuner
28 TSTA START signal for optional tuner
33 ETXD CI-V output (CLONE output)
34 ERXD CI-V input (CLONE input)
35 ESCK EEPROM Clock
36 ESDA EEPROM Data
37 RITD RIT LED
38 TCON Tuner connect detect
40 DISEN LCD OFF
41 DISST LCD driver serial chip enable
42 DISCK LCD driver serial clock
43 DISDA LCD driver serial data
45– KR7–
Key matrix input return
52 KR0
53 PWRS Power control
54 RXS RX control
55 TXS TX control
56 SNDS External SEND control (via ACC socket)
57 BSTB Strobe for shift register of MAIN
58 ASTB1 Strobe (1/2) for M62352GP (D/A)
BAND relay system clock (shift register for RF,
59 MCK
shift register for 1st LO filter)
BAND relay system data (shift register for RF, shift
61 MDAT
register for 1LO filter)
63 ASTB2 Strobe (2/2) for M62352GP(D/A)
64 1CN0 AD9951 (DDS for 1st LO) IO UPDATE
65 3DST AD9833 (DDS for 3rd LO) storobe
66 1DST AD9951 (DDS for 1st LO) strobe
67 MRESL System reset (shift register for MAIN)
DDS system reset (shift register for 1st LO filter,
68 PRESL
AD9951)
SIGNAL DESCRIPTION I\O ACTIVE
O H
O –
I –
O –
O L DSP reset=L
O –
O H USB turn ON=H
O H USB side=H, ACC side=L
I L Reset
I – edge interrrupt
I H USB connect
I L L=ON
O H H: dark, L: bright
O H H: dark, L: bright
O L data latch
O L data=1
I H pulse (DOWN: phase B gain) 47 kΩ pull-up
I H pulse (UP: phase A gain)
I –
I – H=down, L=up
I L
O L
O H –
I H –
O L data latch (output)
IO L –
O H turn on
I H tunet connect
O L L=turn on, H=turn off
O H data transmitting
O – data latch
O H data=1
I H H: key pull down
O H power ON=H
O H RX=H
O H TX=H
O L except ACC SEND TX=L
O H data renewal
O H data renewal
O – data latch
O H data=1
O H data renewal
O – DDS output renewal
O L data transmitting
O L data transmitting
O L main system resetting =L
O L DDS system resetting=L
3 - 5
PULL-UP/
PULL-DOWN
– –
– –
47 kΩ pull-
–
down
– –
47 kΩ pull-
down
– –
47 kΩ pull-
down
–
10 kΩ pull-up
100 kΩ pull-up
–
47 kΩ pull-up
47 kΩ pull-up
47 kΩ pull-up
–
–
47 kΩ pull-up
220 kΩ pull-
–
down
220 kΩ pull-
down
– 47 kΩ pull-up
– 10 kΩ pull-up
100 kΩ pull-up
100 kΩ pull-up
22 kΩ pull-up
10 kΩ pull-up
47 kΩ pull-
down
1 MΩ pull-down
100 kΩ pull-
down
–
–
–
47 kΩ pull-
down
47 kΩ pull-
down
47 kΩ pull-
down
47 kΩ pull-
down
47 kΩ pull-up
–
–
–
–
–
–
–
–
47 kΩ pull-
down
47 kΩ pull-
down