Pll Circuits - Icom IC-2SET Service Manual

4-2-4
APC
CIRCUIT (MAIN
AND
APC
UNITS)
The
APC
circuit
protects the
power module
(IC1)
from
a
mismatched
output load
and
selects
HIGH
and
LOW
output power.
The
output
power
level
from
the
power module
(IC1)
is
detected
at
the
APC
detector
(D10~D12).
When
antenna
impedance
is
matched
at
50
Q,
the detected
level
is
at
a
minimum.
However,
when antenna impedance
is
mismatched,
the detected voltage
is
higher than
when
matched.
When
the
antenna impedance
is
mismatched,
the
base
voltage
of
Q3b
(APC
UNIT)
Is
higher than the other base
voltage
of
Q3a
(reference
voltage).
Q3b
decreases
the
collector
current
of
Q1
using Q2. Collector current of
Q1
is
used
at
the drive amplifiers (Q6,
Q7) on
the
MAIN
UNIT. Hence,
when
the antenna
Impedance
is
mis-
matched,
the output
power
is
decreased.
The
output
power
selecting
circuit
uses the
APC
circuit.
The
PCON
voltage
from
the lO
UNIT
shifts
the
reference
voltage,
changing
the output
power
to
HIGH
or
LOW
1~3.
4-2-5
ANTENNA
SWITCHING
CIRCUIT
(MAIN
UNIT)
When
transmitting,
D7 and
D9
are turned
ON. The
RF
output signal
is
not applied
to
the receiver
circuit,
passing
through
D9 and
C60,
the
low-pass
filter
(L2~L4, C21
~C25) and
then
to
the antenna.
The
low-pass
filter
suppresses
high
harmonic components.
4-3
PLL CIRCUITS
4-3-1
GENERAL
(PLL UNIT)
The PLL
circuit,
using a
one
chip
modulus
prescaler
(IC1),
directly
generates
the transmit
frequency
with the
Tx
VCO
(Q2)
and
the
1st
LO frequency
with the
Rx
VCO
(01).
The modulus
prescaler
(IC1)
sets the
dividing ratio
based
on
serial
data from
the
CPU, and compares
the
phases
of
a
VCO
signal
and the reference
oscillator
frequency.
It
detects the out-of-step
phase and
outputs
it.
The
reference frequency
is
oscillated
at
XI
.
4-3-2
REFERENCE OSCILLATOR
CIRCUIT
(PLL UNIT)
A
reference frequency
is
produced by
the
local oscillator
section
of IC1
and
XI.
C22
provides
frequency
control.
4-3-3
LOOP
FILTER CIRCUIT
(PLL UNIT)
Phase-detected
signals
from
IC1 pin
13 are converted
to
DC
voltage by a
lag-lead
loop
filter
(R17,
R18, C28,
C29).
The frequency
at
which the
VCO
oscillates
is
controlled
by varactor diodes
(D1, D2).
DC
voltage
(PLL
lock
voltage)
is
provided through the buffer amplifier
(06).
01 0
provides
Rx bandpass
filter
tuning.
PLL CIRCUIT
IC1
M54959FP
PLL
OUTPUT
XI
Fig.
3
4-3-4
VCO
CIRCUIT
(PLL UNIT)
IC-2SAT/SET has
2
VCO
circuits for
transmitting
and
receiving. IC1
pins 10
and
11
output control signals
for
selecting the receive
VCO
circuit (Q1,
LI,
D1)
or
transmit
VCO
circuit (02,
L2, D2).
Varactor diodes
(D1,
D2)
provide frequency
control.
The
buffer amplifiers
(Q3~Q5) do
not
affect
the
PLL
output signal
from
VCO
oscillation.
07
selects the
transmit or receive
VCO
circuit.
4-3-5
UNLOCK SENSOR
CIRCUIT
(PLL UNIT)
When
the
PLL
circuit
is
unlocked,
IC1 pin
14
is
"HIGH"
and
the
"HIGH"
signal
is
applied
to
the
CPU
pin
7 as an
unlock
signal.
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