Fcr - Fifo Control Register (Addr = 2, Write Only) - Multitech SocketModem MT5600SMI-32 Developer's Manual

FCR – FIFO Control Register (Addr = 2, Write Only)
The FCR is a write-only register used to enable FIFO mode, clear the RX FIFO and TX FIFO, enable
DMA mode, and set the RX FIFO trigger level.
Bits 7-6 RX FIFO Trigger Level
FCR7 and FCR6 set the trigger level for the RX FIFO (Receiver Data Available) interrupt.
FCR7
0
0
1
1
Bits 5-4 Not used
Bit 3 DMA Mode Select
When FIFO mode is selected (FCR0 = 1), FCR3 selects non-DMA operation (FCR3 = 0) or DMA
operation (FCR3 = 1). When FIFO mode is not selected (FCR0 = 0), this bit is not used (the
modem operates in non-DMA mode in 16450 operation).
DMA Operation in FIFO Mode
RXRDY
than the value in the RX FIFO Trigger Level (IIR0-IIR3 = 4h) or the received character
timeout (IIRO-IIR3 = Ch) has occurred. RXTDY will go inactive when there are no more
characters in the RX FIFO.
TXRDY
FIFO.
Non-DMA Operation in FIFO Mode
RXRDY
go inactive when there are no more characters in the RX FIFO.
TXRDY
inactive when the character is loaded into the TX FIFO Buffer.
Bit 2 TX FIFO Reset
When FCR2 is a 1, all bytes in the TX FIFO are cleared. This bit is cleared automatically by the
modem.
Bit 1 RX FIFO Reset
When FCR1 is a 1, all bytes in the RX FIFO are cleared. This bit is cleared automatically by the
modem.
Bit 0 FIFO Enable
When FCR0 is a 0, 16450 mode is selected and all bits are cleared in both FIFOs. When FCR0
is a 1, FIFO mode (16550A) is selected and both FIFOs are enabled. FCR0 must be a 1 when
other bits in the FCR are written or they will not be acted upon.
Multi-Tech Systems, Inc. SocketModem MT5600SMI Developer's Guide
Chapter 4 – SocketModem Parallel Interface – A Programmer's Description
FCR6 RX FIFO Trigger Level (Bytes)
0 01
1 04
0 08
1 14
will be asserted with the number of characters in the RX FIFO us equal to or greater
will be asserted when there are one or more empty (unfilled) locations in the TX
TXRDY will go inactive when the TX FIFO is completely full.
will be asserted when there are one or more characters in the RX FIFO. RXRDY will
will be asserted when there are no characters in the TX FIFO. TXRDY will go
21