Parallel Host Bus Timing; Parallel Host Bus Timing Table - Multitech SocketModem MT5600SMI-32 Developer's Manual

Parallel Host Bus Timing

Parallel Host Bus Timing Table

Symbol Parameter
t
Address Setup
AS
t
Address Hold
AH
t
Chip Select Setup
CS
t
Chip Select Hold
CH
t
RD Strobe Width
RD
t
Read Data Delay
DD
t
Read Data Hold
DRH
t
Address Setup
AS
t
Address Hold
AH
t
Chip Select Setup
CS
t
Chip Select Hold
CH
t
WT Strobe Width
WT
t
Write Data Setup (see Note 4)
DS
t
Write Data Hold (see Note 5)
DWH
Notes:
1. When the host executes consecutive Rx FIFO reads, a minimum delay of 2 times the internal CPU
clock cycle plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of RD to the falling
edge of the next Host Rx FIFO RD clock.
2. When the host executes consecutive Tx FIFO writes, a minimum delay of 2 times the internal CPU
clock cycle plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of WT to the
falling edge of the next Host Tx FIFO WT clock.
t t t
= + 15 ns.
3. RD' WT CYC
t
.
4 DS is measured from the point at which both CS and WT are active.
t
.
5 DWH is measured from the point at which either CS and WT become active.
6. Clock Frequency = 28.224 MHz clock.
Multi-Tech Systems, Inc. SocketModem MT5600SMI Developer's Guide
Min
READ (See Notes)
5
10
0
10
45
-
5
WRITE (See Notes)
5
15
0
10
75
-
5
Chapter 3 – Electrical Characteristics
Max Units
- ns
- ns
- ns
- ns
- ns
25 ns
- ns
- ns
- ns
- ns
- ns
- ns
20 ns
- ns
16