Epson EPL-9000 Service Manual page 78

2.2.1.1 Reset Circuit
The entire system (the CPU and the external devices) can be initialized if the RESET signal (CPU
pin 113) are active
a voltage level less than 4.25 V is detected.
L
+
c
2.2.1.2 Bus
The CPU outputs the R/W (read/write) signal, AS (address strobe) signal, and the BE(),
BE1, BE2, and BE3 signals (byte
to generate the RD (read strobe) signal, WR (write strobe) signal, and READY signal.
CPU
(ICI)
2-26
This circuit uses an
reset time is approximately 128 ms.
4
OUT
Figure 2-38. Reset Circuit
Circuit
to the
AS
BE()-3
- u
—
Bus
Figure 2-39. Bus Control Circuit
to monitor the supply voltage if
The
WR
Bus
Service
uses these signals
Rev.