Private Memory Interconnect (Pmi); Location Of The Msvll-Jd, -Je Memory; Pmi/Q22-Bus Interface - Digital Equipment MicroPDP-11 Technical Manual

MicroPDP-11 Base Systems
2.10.3 Private Memory Interconnect (PMI)
The MSVll-JD, -JE memories are designed for Q22-Bus systems and support the
PMI protocol of the KDJll-BF processor. The PMI bus is specifically designed for
and used in MicroPDP-ll/83 Q22-Bus systems.
The MicroPDP-ll/83 systems use the KDJll-BF CPU module, one or more
MSVll-JD or MSVll-JE memory modules, and a selection of Q22-Bus compatible
devices. Data transfers between the KDJll-BF CPU and the MSVll-JD or -JE
memory using the PMI protocol resident on the CPU. All other communications,
whether originated by the CPU or other bus masters, use the Q22-Bus protocol.
2.10.4 Location of the MSV11-JD, -JE Memory
The location of the MSVll-JD, -JE in the BA23 backplane determines the protocol
used between the KDJll-BF processor and the memory module (Figure 2-10). To
use the PMI protocol, the MSVll-JD, -JE must be located immediately in front
(lower slot number) of the CPU; otherwise, the memory and CPU communicate
with the Q22-Bus protocol. There must be no open slot between memory and the
CPU.
CAUTION
Static charges can damage the MOS memory chips. Be careful
how you handle the module and where you lay it down.
When you install or remove the memory module, make sure
there is no dc voltage applied to the module.
If the green LED is on, the module is receiving +5 V or +5 VBB power. The
power source must be off before you remove or replace a memory module.
2-38
MSV11-J
MEMORY
KDF11-BF
CPU
Q22-BUS
DEVICES
Figure 2-10 PMI/Q22-Bus Interface