Sony SDP-EP70 Service Manual page 55

Pin Name
Pin No.
92
GNDD
93
D6
94 D7
95
D8
96
D9
97
VDDQ
98
GNDQ
99 GNDD
100
D10
101 D11
102
VCCD
103
D12
104 D13
105
GNDD
106
D14
107
D15
108
D16
109 D17
110
GNDD
111
D18
112
D19
113
VCCD
114 D20
115
D21
116
GNDD
117
D22
118
D23
119 MODC/NMI
120
MODB/IRQB
121
MODA/IRQA
122
GNDCK
123
CKOUT
124 VCCCK
125
RESET
126
CKP
127
VCCP
128
PCAP
129 GNDP
130 PLOCK
131
PINIT
132
XTAL
• Abbreviation
PLL : Phase Locked Loop
I/O
– Power supply for data bus
I/O
I/O
Data input/output to S-RAM
I/O
I/O
Power supply for interrupt/mode control
–
–
Ground for interrupt/mode control
– Ground for data bus
I/O
Data input/output to S-RAM
I/O
– Power supply for data bus
I/O
Data input/output to S-RAM
I/O
– Ground for data bus
I/O
I/O
Data input/output to S-RAM
I/O
I/O
– Ground for data bus
I/O
Data input/output to S-RAM
I/O
–
Power supply for data bus
I/O
Data input/output to S-RAM
I/O
–
Ground for data bus
I/O
Data input/output to S-RAM
I/O
Mode select C/Non-maskable interrupt request input
I
I
Mode select B/External interrupt request input
I
Mode select A/External interrupt request/stop recovery input
Ground for clock
–
O
Output clock output (Not used)
– Power supply for clock
I Rest input
I Output clock polarity control input
– Power supply for analog PLL
I
PLL filter capacitor input
Ground for analog PLL
–
O Phase and frequeny locked output
I
PLL initialization input (Fixd at "L")
O Crystal output (Not used)
– 70 –
Function