Sony SDP-EP70 Service Manual page 56

• IC1006 Serial Communication Format Converter (CXD8751Q)
Pin Name
Pin No.
1 LAC3
2
—
3 WSR
4 GPIO0
5 —
6
VCC
7 —
8 SCKR
9 SDI0
10
DI2
11
DI3
12 DIN
13 BCKI
14
LRCK
15 DCK
16 MCK
17 GND
18
BCKO
19
LRCKO
20 RLRCK
21 LRPH
22
MCPH
23
—
24 HALM
25 DO1
26 SRD
27
—
28
VCC
29 —
30
SC1
31
DO4
32 HDO4
33
HDI1
34 H2X1
35
HIIS
36 STD
37 SC2
38
SCK
39
GND
40 DTI
41 SC0
42 TXD
43
RXD
44 —
I/O
Decoder select input H: MPEG decode/L: AC-3 decode
I
– Not used
O LR clock output for DSP56009 (MPEG: 4 Fs/AC-3: 1 Fs) H: L channel
O Frame sync pulse output (1 Fs) for write data to DSP56009
– Not used
– +5V power supply
–
Not used
O Clock output for data write to DSP56009 (MPEG: 256 Fs/AC-3: 64 Fs)
Write data (DSP56009) output
O
I
Fix at "L"
I
I
Data input to DSP56002
Bit clock input for Data input from DSP56002
I
I L/R ch switching clock input for Data input from DSP56002
I
Master clock delay input
I Master clock input
— Ground
64 Fs clock output (Not used)
O
O 1 Fs clock output (Not used)
O
1 Fs clock output (Not used)
L/R ch clock phase control input (Fix at "L")
I
I 256 Fs master clock phase control input (Fix at "L")
– Not used
I
Digital signal processor select mode input (Fix at "L")
O Not used
Write data (DSP56002) 1 bit delay output (L: DI2, H: DIN)
O
–
Not used
– +5V power supply
– Not used
Frame sync pulse output for write data to DSP56002
O
O Not used
I
Fixed at "L"
I Digital signal processor data input select input (L: DI2, H: DIN)
I Fixed at "L"
I L/R ch clock timing select (Fixed at "L")
I Read data (DSP56002) input
O Word sync pulse output (8 Fs) for read data to DSP56002
Clock output (256 Fs) for read data to DSP56002
O
–
Ground
I Fixed at "L"
O Bit clock output for write data to DSP5602
O Frame sync pulse output (1 Fs) for read data to DSP56002
O L/R ch clock output for wirte data to DSP56002
–
Not used
– 71 –
Function