Sharp LC-52XS1E Service Manual page 73

Pin No. Pin Name
27 MODE2
30 /PDWN
31 PRBS
10, 11, 12, 16, Reserved
28, 32
23 Reserved
29, 33, 109 N/C
3, 13, 82, 93, VCC
104, 113, 125,
137
4, 14, 83, 94, GND
105, 114, 126,
138
43, 49, 55, 61, LVCC
67
37, 42, 48, 54, LGND
60, 66, 72
35, 74 PVCC
34, 36, 73, 75 PGND
19.IC7002 (RH-iXC331WJQZQ)
This is a monitor microprocessor, which receives the remote control light, controls the CEC signal, detects the keys, and detects the OPC. It also
detects the errors relating to the power supply within the IF PWB and controls the power supply of the monitor.
20.IC7006 (VHiBR24L04F-1Y)
This is an EEPROM, in which the portion of the data processed by IC7002 is stored.
21.IC5802 (VHiLTC1154+-1Y)
This is a power supply IC, which supplies 5V for the optional wireless transmission unit. It also detects short circuits and has the thermal shutdown
function.
22.IC5901 (VHiBD9045FV-1Y)
This is a DC/DC converter, which inputs 15V from the power supply unit and generates 5V and 3.3V used within the IF PWB.
2ch DC/DC Converter
Pin No. Pin Name
1 OUTL2
2 DGND2
3 SW2
4 OUTH2
5 BOOT2
6 CL2
7 N.C.
8 VREG5
9 CL1
10 BOOT1
11 OUTH1
12 SW1
13 DGND1
14 OUTL1
15 GND
16 TM1
17 SS1
I/O
I Distribution, DDR function enable.
The use of these multi-function depends on the setting of MODE<1:0>.
MODE<1:0>=HH(Single-in/Single-out Mode)
H: Distribution function enable.
L: Distribution function disable.
MODE<1:0>=HL(Single-in/Single-out Mode)
H: DDR (Double Edge input) function enable.
L: DDR (Double Edge input) function disable.
I H: Normal operation,
L: Power down (all outputs are Hi-Z)
I PRBS generator is active when MODE <1:0> = LL (Dual-in/Dual-out mode)
H: PRBS generator is enable. Pattern is PRBS-23.
L: Normal Operation
I Must be tied to GND.
I Must be Open.
Must be Open.
- Power Supply Pins for TTL inputs, output and digital circuitry.
- Ground Pins for TTL inputs, outputs and digital circuitry.
- Power Supply Pins for LVDS Outputs.
- Ground Pins for LVDS Outputs.
- Power Supply for PLL circuitry.
- Ground Pin for PLL circuitry.
I/O
O Low side FET gate drive terminal 2
- Low side FET source terminal 2
I High side FET source terminal 2
O High side FET gate drive terminal 2
- OUTH2 driver power supply terminal
I Over-current detection setting terminal 2
- No Connection
- The REG output for FET drive
I Over-current detection setting terminal 1
- OUTH1 driver power supply terminal
O High Side FET gate drive terminal 1
I High Side FET source terminal 1
- Low side FET source terminal 1
O Low side FET gate drive terminal 1
- Ground terminal
- Output 1 OCP and an OVP timer latch setting terminal
- Soft starting time setting terminal 1
Pin Function
Pin Function
5 – 14
LC-52XS1E/RU/LC-65XS1E/RU