Sharp LC-52XS1E Service Manual page 68

LC-52XS1E/RU/LC-65XS1E/RU
Pin No. Pin Name
B9 SD
B7 TXD
B8 RXD
H9 TEST
C8, G2, VDDIO
G8
B2, E8, H3 VDDCORE
B6, C2, VSS
D8, F2,
H2, H8
10.IC6608 (VHiBR24L64F-1Y)
This is an EEPROM, in which the portion of the data processed by the IC6201 is stored.
11.IC6651 (VHi29GL064N-1Q)
This is a 64Mb NOR flash, in which the software of IC6201 is stored.
64M FLASH MEMORY
Pin No. Pin Name
3-12,15, 18-26, A21-A0
31,54
35-42, 44-50 DQ14-DQ0
51 DQ15/A-1
32 CE#
34 OE#
13 WE#
16 WP#/ACC
14 RESET#
17 RY/BY#
53 BYTE#
43 VCC
33, 52 VSS
1, 2, 27, 28, 30, NC
55, 56
29 VIO
12.IC6652 (RH-iXC623WJQZQ)
This is a 1Gb NAND flash, in which the IC6201's data and the preinstalled pictures of the wall picture function are stored.
1Gb FLASH MEMORY
Pin No. Pin Name
29-32, 41-44 IO7 - IO0
16 CLE
17 ALE
9 CE#
8 WE#
18 RE#
19 WP#
I/O
O Front end shutdown signal
O The transmitting data signal of UART
I The receiving data signal of UART
I Test Mode
- I/O Power Supply (1.8-3.3v)
- Core power supply (1.8V)
- Ground
I/O
I 22 Address inputs
O 15 Data input/output
O DQ15 (Data input/output, at LSB word mode), A-1(LSB-Address Input, at byte mode)
I Chip Enable input
I Output Enable input
I Write Enable input
I Hardware Write Protect input/Programming Acceleration input
I Hardware Reset Pin input
I Ready output ; indicates the status of the Burst read./Busy output
I Selects 8-bit or 16-bit mode
- Device Power supply (3.0V)
- Device Ground
- Pin Not Connected Internally
- Output Buffer Power
I/O
O Data Inputs / Outputs
The IO pins allow to input command, address and data and to output data during read / pro-
gram operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O
buffer float to High-Z when the device is deselected or the outputs are disabled.
O COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising
edge of Write Enable (WE).
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising
edge of Write Enable (WE).
I CHIP ENABLE
This input controls the selection of the device. When the device is busy CE low does not dese-
lect the memory.
I WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on
the rise edge of WE.
I READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus.
Data is valid tREA after the falling edge of RE which also increments the internal column
address counter by one.
I WRITE PROTECT
The WP pin, when Low, provides an Hardware protection against undesired modify (program /
erase) operations.
Pin Function
Pin Function
Pin Function
5 – 9
Remarks
Positive logic
Positive logic
Positive logic
Usual '0' Fixation