Sharp LC-52XS1E Service Manual page 62

LC-52XS1E/RU/LC-65XS1E/RU
Pin No. Pin Name
24 I2CSEL/INT#
50 RSVDL
Control Pins
11 RESET#
13 LSCL/EPSEL1
12 LSDA/EPSEL0
CEC Pins
41 CEC_A
40 CEC_D
Differential Signal Data Pins
30 RX0+
29 RX0-
33 RX1+
32 RX1-
35 RX2+
34 RX2-
28 RXC+
27 RXC-
6 TX0+
7 TX0-
3 TX1+
4 TX1-
1 TX2+
2 TX2-
8 TXC+
9 TXC-
10 EXT_SWING
Power and Ground Pins
14, 15, 16, AGND
17, 18, 19,
20, 21, 43,
44, 45, 46,
47, 55, 56
5, 26, 36 AVCC18
22, 48 DVCC18
23, 49 DGND
31, 42 AVCC33
I/O
I2C Selection input/ Interrupt output pin.
The SiI9181A has two modes of operation: I2C control and Standalone. The mode is determined by the
level of the I2CSEL/INT pin at the rising edge of RESET#. A high indicates I2C mode, and a low indicates
Standalone mode.
In I2C control mode, all functions are controlled and observed with I2C registers using the pins LSCL/
I/O
EPSEL1 and LSDA/EPSEL0 as the local I2C bus.
In Standalone mode, the external pins LSCL/ EPSEL1 and LSDA/ EPSEL0 are use to determine whether
the SiI9181A is in Normal mode or Standby mode.
After reset, this pin becomes the Interrupt output.
This is an open-drain output and requires an external pull-up.
--- Reserved for use by Silicon Image and must be tied low.
Reset Pin (Active LOW). Certain configuration inputs are latched when RESET# transitions from low to
I
high.
Local I2C Clock / External Port Select 1. When I2CSEL is high, this becomes the Local I2C bus clock pin,
I LSCL. When I2CSEL is low, this becomes the external port select pin, EPSEL1. True open drain, so does
not pull to ground if power not applied. An external pull-up is required.
Local I2C Data / External Port Select 0. When I2CSEL is high, this becomes the Local I2C bus data pin,
I/O LSDA. When I2CSEL is low, this becomes the external port select pin, EPSEL0. True open drain, so does
not pull to ground if power not applied. An external pull-up is required.
HDMI compliant CEC I/O used to interface to CEC devices.
CEC electrically compliant signal. This pin connects to the CEC signal of all HDMI connectors in the sys-
I/O tem.
As an input, the pad acts as a LVTTL Schmitt triggered input and is 5V tolerant. As an output, the pad acts
as an NMOS driver with resistive pull-up. This pin has an internal pull-up resistor.
CEC interface to local system. True open-drain. An external pull-up is required. This pin typically connects
I/O
to the local CPU.
I
I
I
TMDS input data pairs.
I
I
I
I
TMDS input clock pair.
I
O
O
O
TMDS output data pairs.
O
O
O
O TMDS output clock pair.
O
O Voltage Swing Adjust. A resistor tied from this pin to AVCC18 determines the amplitude of the voltage
swing. The recommended value is 750 Ω.
--- Analog GND.
--- Analog VCC. Connect to 1.8V supply.
--- Digital VCC. Connect to 1.8V supply.
--- Digital GND.
--- Analog VCC. Connect to 3.3V supply.
Pin Function
5 – 3