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Data Register
Word Data Register
Even Data Register
Odd Data Register
Odd Data Register
Error/Feature Register
Error/Feature Register
Error/Feature Register
4.5.2. Error Register (Address—1F1[171]; Offset 1, 0Dh Read Only)
This register contains additional information about the source of an error when an error is indicated in bit 0 of the
Status register. The bits are defined as follows:
D7
D6
BBK
UNC
This register is also accessed on data bits D15-D8 during a write operation to offset 0 with -CE2 low and -CE1 high.
Bit 7 (BBK)
This bit is set when a Bad Block is detected.
Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
Bit 5
This bit is 0.
Bit 4 (IDNF)
The requested sector ID is in error or cannot be found.
Bit 3
This bit is 0.
Bit 2 (Abort)
This bit is set if the command has been aborted because of a CompactFlash Memory Card status condition:
(Not Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1
This bit is 0.
Bit 0 (AMNF)
This bit is set in case of a general error.
4.5.3. Feature Register (Address—1F1[171]; Offset 1, 0Dh Write Only
This register provides information regarding features of the CompactFlash Memory Card that the host can utilize.
This register is also accessed on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1
high.
4.5.4. Sector Count Register (Address—1F2[172]; Offset 2)
This register contains the number of sectors of data requested to be transferred on a read or write operation between
the host and the CompactFlash Memory Card. If the value in this register is zero, a count of 256 sectors is specified.
If the command was successful, this register is zero at command completion. If not successfully completed, the
register contains the number of sectors that need to be transferred in order to complete the request.
®
CompactFlash
Memory Card Product Manual, Rev. 10.0 © 2002 SANDISK CORPORATION
Table 4-6. Data Register
CE2-
CE1-
0
0
1
0
1
0
0
1
1
0
0
1
0
0
D5
D4
0
IDNF
ATA Drive Register Set Definition and Protocol
A0
Offset
X
0,8,9
0
0,8
1
9
X
8,9
1
1, Dh
X
1
X
Dh
D3
D2
0
ABRT
Data Bus
D15-D0
D7-D0
D7-D0
D15-D8
D7-D0
D15-D8
D15-D8
D1
D0
0
AMNF
4-5
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