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ATA Drive Register Set Definition and Protocol
4.4. True IDE Mode Addressing
When the CompactFlash Memory Card is configured in the True IDE Mode the I/O decoding is as listed in
Table 4-5.
-CE2
1
1
1
1
1
1
1
1
0
0
4.5. ATA Registers
NOTE: In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset
address may be accessed at its normal address and also the corresponding even address (normal address -1)
using data bus lines (D15-D8) when -CE1 is high and -CE2 is low unless -IOIS16 is high (not asserted) and
an I/O cycle is being performed.
4.5.1. Data Register (Address—1F0[170];Offset 0, 8, 9)
The Data Register is a 16-bit register, and it is used to transfer data blocks between the CompactFlash Memory Card
data buffer and the Host. This register overlaps the Error Register. The table below describes the combinations of
data register access and is provided to assist in understanding the overlapped Data Register and Error/Feature
Register rather than to attempt to define general PCMCIA word and byte access modes and operations. See the
PCMCIA PC Card Standard Release 2.0 for definitions of the Card Accessing Modes for I/O and Memory cycles.
NOTE: Because of the overlapped registers, access to the 1F1, 171 or offset 1 are not defined for word (-CE2 = 0
and -CE1 = 0) operations. SanDisk products treat these accesses as accesses to the Word Data Register. The
duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed by
the socket.
4-4
Table 4-5. True IDE Mode I/O Decoding
-CE1
A2
A1
A0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
®
CompactFlash
Memory Card Product Manual, Rev. 10.0 © 2002 SANDISK CORPORATION
-IORD=0
-IOWR=0
Even RD Data
Even WR Data
Error Register
Features
Sector Count
Sector Count
Sector No.
Sector No.
Cylinder Low
Cylinder Low
Cylinder High
Cylinder High
Select Card/Head
Select Card/Head
Status
Command
Alt Status
Device Control
Drive Address
Reserved
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