Table of Contents
Advertisement
Item
Data Setup before -IOWR
Data Hold following -IOWR
-IOWR Width Time
Address Setup before -IOWR
Address Hold following -IOWR
-CE Setup before -IOWR
-CE Hold following -IOWR
-REG Setup before -IOWR
-REG Hold following -IOWR
-IOIS16 Delay Falling from Address
-IOIS16 Delay Rising from Address
1.All timing in ns.
2.The maximum load on -IOIS16 is 1 LSTTL with 50 pF total load.
3.3.11. True IDE Mode
The following sections provide valuable information for the True IDE mode.
3.3.11.1. Deskewing
The host shall provide cable deskewing for all signals originating from the device. The device shall provide cable
deskewing for all signals originating at the host.
All timing values and diagrams are shown and measured at the connector of the selected device.
3.3.11.2. Transfer Timing
The minimum cycle time supported by devices in PIO mode 3, 4 and Multiword DMA mode 1, 2 respectively shall
always be greater than or equal to the minimum cycle time defined by the associated mode, e.g., a device supporting
PIO mode 4 timing shall not report a value less than 120 ns. The minimum cycle time defined for PIO mode 4
timings.
NOTE: PIO Modes greater than 1 are not supported in Industrial Temperature products.
Register Transfers
Figure 3-5 defines the relationships between the interface signals for register transfers.
For PIO modes 3 and above, the minimum value of t
list. Table 3-8 defines the minimum value that shall be placed in word 68.
®
CompactFlash
Memory Card Product Manual, Rev. 10.0 © 2002 SANDISK CORPORATION
Table 3-11. I/O Write Timing Specification
Symbol
t
(IOWR)
su
t
(IOWR)
h
t
(IOWR)
w
t
A(IOWR)
su
t
A(IOWR)
h
t
CE(IOWR)
su
t
CE(IOWR)
h
t
REG(IOWR)
su
t
REG(IOWR)
h
t
IOIS16(ADR)
df
t
IOIS16(ADR)
dr
is specified by word 68 in the IDENTIFY DEVICE parameter
0
CompactFlash Memory Card Interface Description
IEEE Symbol
Min
tDVIWL
60
tlWHDX
30
tlWLIWH
165
tAVIWL
70
tlWHAX
20
tELIWL
5
tlWHEH
20
tRGLIWL
5
tlWHRGH
0
tAVISL
tAVISH
Max
35
35
3-15
Advertisement
Table of Contents
