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2.9.3
Signal Descriptions
Table 2-15
PCI0643 Signal Descriptions
Signal
2NDIDEEN#/
87
DAMCK0
2NDIOR#
77
2NDIOW#
78
AD[31:0]
7-14,
17-20,
23-26,
28-35,
42-49
C/BE[3:0]#
3-6
DMACK1#
88
DCHRDY
76
DCS0#
55
DCS1#
56
DCS2#
80
DCS3#
79
Pin
Type
B/T
Secondary IDE Channel Enable and DMA Request
Acknowledge 0 This signal is used in response to DMARQ0
to wither acknowledge that data has been accepted, or that
data is available. At power-up, the state of this signal is used
to enable or disable the secondary channel.
T/O
Secondary Channel Disk I/O Read. This is an active low
output which enables data to be read from the drive. The
duration and repetition rate of DIOR# cycles is determined by
PCI0643 programming. DIOR# is driven high when inactive.
T/O
Secondary Channel Disk I/O Write This is an active low
output that enables data to be written to the drive. The duration
and repetition rate of DIOW# cycles is determined by PCI0643
programming. DIOW# is driven high when inactive.
B/T
Address and Data. Address and data are multiplexed on the
same PCI pins.
phase followed by one or more data phases. PCI supports
both read and write bursts. The address phase is the clock
cycle in which FRAME# is asserted.
phase, AD[31:0] contain a physical address (32 bits). For I/O,
this is a byte address. For configuration and memory, it is a
Dword address. During data phases, AD[31:24] contain the
least significant byte (lsb) and AD[31:24] contain the most
significant byte (msb). Write data are stable and valid when
TRDY# is asserted. Data are transferred during those clocks
where both IRDY# and TDY# are asserted.
B/T
Byte Enable bits 0 through 3. These form the host CPU
address bus. These inputs are active low and specify which
bytes are valid for host read/write data transfers.
B/T
This signal normally is used in response to DMARQ1 to either
acknowledge that data has been accepted.
I
Disk Ready. This is an active high input that indicates that
the IDE disk drive has completed the current command cycle.
A 1KΩ pull-up resistor is recommended.
O
Disk Chip Select 0. Drive chip select for 1Fx.
O
Disk Chip Select 1. Drive chip select for 3F6.
O
Disk Select 2. This is used to select the second IDE port
command registers in the drive.
O
Disk Select 3. This is used to select the second IDE port
auxiliary register.
Description
A bus transaction consists of an address
During the address
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