Acer AcerNote 970 Service Manual page 84

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Table 2-4
V3-LS Pin Descriptions (continued)
Pin Name
PCI Interface (continued)
FRAME#
H_PCICLK
H_PCIRST#
IDSEL
IRDY#
PCI_LOCK#
PAR
PCI_INT[D:A]#
PERR#
SERR#
STOP#
TRDY#
Power and Ground
VSS
VSSCORE
VCCCORE
VCCISA
VCCPCI
Pin No.
Type
117
I/O
CYCLE FRAME#: Cycle Frame is driven by the current initiator
and indicates the start and duration of the transaction. FRAME#
is deasserted to indicate that the initiator is ready to complete
the final data phase. A transaction may consist of one or more
data transfers between the current initiator and the currently-
addresses target.
99
I
PCI CLOCK: 33/25 MHz clock for the PCI bus.
154
I
PCI RESET: V3-LS reset input.
104
I
ID SELECT: ID Select for PCI interrupts.
118
I/O
INITIATOR READY#: This indicates the bus master's state of
readiness to complete the current data phase. During a write,
IRDY# shows that valid data is present. During a read, it
indicates the bus master's readiness to accept data. IRDY# is
used in conjunction with TRDY#.
152
I
PCI LOCK#: Used for locking ISA resources.
124
l/O
PARITY: All PCI agents require parity generation.
148:151
I
PCI INTERRUPTS [D:A]#: These inputs from PCI devices are
shareable, level sensitive (active low) interrupt request. They
can be mapped to ISA IRQx through registers PINTM-1 and
PINTM-2.
122
I
PARITY ERROR#: This input indicates a data parity error. It
may be pulsed active by any agent that detects an parity error
condition.
123
I
SYSTEM ERROR#: This input may be pulsed active by any
agent that selects any system error condition.
121
I/O
STOP#: This allows the master to stop the bus transaction to
the current target device.
119
I/O
TARGET READY#: This indicates the ability of the target device
to complete the current data phase of the bus transaction.
During a read phase, TRDY# indicates that the valid data is
present. During a write phase, it indicates that the device is
prepared to accept data
10, 21, 33, 47, 85, 93, 106, 113, 125,
132, 152, 159, 173
153
155
5, 19, 36, 63, 165
98, 111, 128, 139
Description
GND
VSS
GND
VSSCORE
PWR
VCCORE
PWR
VCCISA
PWR
VCCPCI

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