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Table 2-4
V3-LS Pin Descriptions (continued)
Pin Name
ISA Interface (continued)
GPEXT#
IOCHCK#
IOCHRDY
IOCS16#
IOR#
IOW#
IRQ[15,14,12:3,1]
MASTER#
MEMCS16#
MEMR#
MEMW#
REFRESH#
ROM_KB_CS#
RW_RTC
SA[23:0]
SBHE#
Pin No.
Type
65
O
GENERAL PURPOSE OUTPUT EXTENSION: The GPEXT# is
pulsed (low) when register GPEXT_LB is being written. The
value being written to GPEXT_LB and the value previously
latched in GPEXT_HB will be driven onto SD[7:0] and SD[15:8]
respectively to extend by up to 16 general purpose outputs. An
external 8-bit or 16-bit flip-flop should be used to latch the SD-
bus on the rising (trailing) edge of GPEXT#.
87
I
UO CHANNEL CHECK: This input indicates a parity error from
some device on the AT bus. This pin is multiplexed with
ATFLOAT#.
14
l/O
UO CHANNEL READY: When this input is driven low, it
indicates that the device on the AT bus currently being
accessed requires additional time to complete the cycle.
9
I/O
l/O CHIP SELECT 16#: This input from the AT bus indicates
that the current access is to a 1 6-bit l/O device.
2
I/O
I/O READ#: This output to the AT bus indicates an l/O Read
cycle.
1
I/O
I/O WRITE#: This output to the AT bus indicates an l/O Write
cycle.
70, 71,
I
INTERRUPT REQUEST: ISA bus interrupt requests.
72:82
88
I
MASTER#: This input from the AT bus indicates that a slot
master has taken control of the AT bus.
11
I/O
MEMORY CHIP SELECT 16-BIT#: This input from the AT bus
indicates that the current access is to a 16-bit memory device.
13
I/O
MEMORY READ#: This output to the AT bus indicates a
Memory Read cycle to any valid AT bus address.
12
I/O
MEMORY WRITE#: This output to the AT bus indicates a
Memory Write cycle to any valid AT bus address.
84
I/O
REFRESH#: This output drives the AT bus to indicate a
Memory Refresh cycle.
66
O
Combined system BIOS, keyboard, and chip select output.
67
O
RTC READ/WRITE: This output should be connected to the
RW_RTC input of an 14681 8-type or equivalent RTC.
15:18,
I/O
SLOT ADDRESS[23:0]: These signals are decoded from
20, 22,
AD[31:0] and BE[3:0]# of PCI bus. These signals will become
23:32,
inputs during ISA master cycles and will be outputs during all
34, 35,
other cycles.
37:42
6
I/O
SLOT BYTE HIGH ENABLE#: This output to the AT bus
indicates a data transfer on the high byte of the SD bus.
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