M1531 Signal Descriptions - Acer 390 Series Service Manual

2.2.1.3 Signal Descriptions
Table 2-3

M1531 Signal Descriptions

Signal Type
Host Interface 3.3V/2.5V
A[31:3] I/O
Group A
BEJ[7:0] I
Group A
ADSJ I
Group A
BRDYJ O
Group A
NAJ O
Group A
AHOLD O
Group A
EADSJ O
Group A
BOFFJ O
Group A
HITMJ I
Group A
MIOJ I
Group A
DCJ I
Group A
WRJ I
Group A
HLOCKJ I
Group A
CACHEJ I
Group A
2-24
Host Address Bus Lines. A[31:3] have two functions. As inputs, along with
the byte enable signals, these pins serve as the address lines of the host
address bus which define the physical area of memory or I/O being accessed.
As outputs, the M1531 drives them during inquiry cycles on behalf of PCI
masters.
Byte Enables. These are the byte enable signals for the data bus. BEJ[7]
applies to the most significant byte and BEJ[0] applies to the least significant
byte. They determine which byte of data must be written to the memory, or
are requested by the CPU. In local memory read and line-fill cycles, these
inputs are ignored by the M1531.
Address Strobe. The CPU will start a new cycle by asserting ADSJ first. The
M1531 will not precede to execute a cycle until it detects ADSJ active.
Burst Ready. The assertion of BRDYJ means the current transaction is
complete. The CPU terminates the cycle by receiving 1 or 4 active BRDYJs
depending on different types of cycles.
Next Address. This signal is asserted by the M1531 to inform the CPU that
pipelined cycles are ready for execution.
CPU AHold Request Output. It connects to the input of CPU's AHOLD pin
and is actively driven for inquiry cycles.
External Address Strobe. This signal is connected to the CPU EADSJ pin.
During PCI cycles, the M1531 asserts this signal to proceed snooping.
CPU Back-Off. If BOFFJ is sampled active, CPU will float all its buses in the
next clock. M1531 asserts this signal to request CPU floating all its output
buses.
Primary Cache Hit and Modified. When snooped, the CPU asserts HITMJ to
indicate that a hit to a modified line in the data cache occurred. It is used to
prohibit another bus master from accessing the data of this modified line in
the memory until the line is completely written back.
Host Memory or I/O. This bus definition pin indicates the current bus cycle is
either memory or input/ output.
Host Data or Code. This bus definition pin is used to distinguish data access
cycles from code access cycles.
Host Write or Read. When WRJ is driven high, it indicates the current cycle is
a write. Inversely, if WRJ is driven low, a read cycle is performed.
Host Lock. When HLOCKJ is asserted by the CPU, the M1531 will recognize
the CPU is locking the current cycles.
Host Cacheable. This pin is used by the CPU to indicate the system that CPU
wants to perform a line fill cycle or a burst write back cycle. If it is driven
inactive in a read cycle, the CPU will not cache the returned data, regardless
of the state of KENJ.
Description
Service Guide