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Supports mixed FPM (fast page mode) and EDO (extended data output) DRAM
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Slow/self refresh support, including hidden, staggered, CAS-before-RAS refresh or RAS
only refresh
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Dedicated DRAM memory address and data busses
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5-2-2-2 burst read cycles with 60-ns EDO DRAM at 66-MHz
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6-3-3-3 page-hit and 10-3-3-3 page-miss burst-read cycles with 60-ns standard DRAM at
66-MHz
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Two less wait-states in the lead-off cycle for pipeline access
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Write-buffers for CPU generated DRAM cycles
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Supports read reordering
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Support for ROM shadowing
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SMM RAM size from 32 Kbyte to 128 Kbyte. Easy SMI code copying to SMM RAM in
normal memory mode
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PCI Local Bus native architecture
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Supports 32-bit PCI Local Bus
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Supports both 3.3-V and 5-V PCI
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Provides synchronous interface between the CPU bus and the PCI bus
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PCI Local Bus revision 2.01 compliant
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Supports Mobile PCI specification
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Supports PCI burst cycles
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Maximum 5 PCI masters and 4 PCI slots
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Integrated PCI bus arbiter with rotating priority
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PCI parity and system error support
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PCI-to-ISA memory post-write - PCI interrupt steering
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Intelligent power management through clock scaling
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Docking station support
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