Table of Contents
Advertisement
Table 2-3
V2-LS Pin Descriptions
Pin Name
Pin No.
PCI Interface (continued)
PCICLK
96
PCIRST#
90
V1-LS/V2-LS Interface
ADOE#
71
ADPAR_EVEN
68
ADPAR_ODD
70
BD[7:0]
88:83, 81,
80
BDCTL[2:0]
79:77
DECBUF
72
INCBUF
73
PCIMSTR#
89
Power and Ground
VCCC
76, 185
VCCCPU
7, 28, 48, 69, 158, 177, 196
VCCDRAM
141
VCCPCI
101, 121
VSSIO
5, 21, 39, 55, 82, 95, 106, 116,
126, 139, 156, 175, 194,
VSSC
74, 183
Type
I
PCI CLOCK INPUT: This is a clock generated by V1-LS and is
derived from LCLK and delayed by 1/2+ clock cycle or is the
inversion of LCLK.
I
PCI RESET: This signal is the PCI reset signal
I
AD BUS OUTPUT ENABLE#: When this signal is active, V2-LS
drives the PCI AD bus AD[31:0].
l/O
AD BUS PARITY: This signal indicates the PCI AD Bus parity
when V2-LS samples PCI AD Bus.
l/O
AD BUS PARITY: Output to V1-LS to indicate PCI AD Bus
parity.
I/O
BURST DATA BUS [7:0]: This 8-bit bus carries different
information during various phases.
I
BDCTL[2:0]: Datapath control signals from V1-LS
-- I
DECREMENT WRITE BUFFER COUNTER: This input is used
to decrease the pointer on the 8 level write buffer.
I
INCREMENT WRITE BUFFER COUNTER: This input is used to
increase the pointer on the 8 level write buffer.
I
PCI MASTER#: This output from V1-LS indicates that Vesuvius
is responding to a PCI master cycle.
Description
PWR
VCCC
PWR
VCCCPU
PWR
VCCDRAM
PWR
VCCPCI
GND
VSSIO
GND
VSSC
Advertisement
Table of Contents
