Advanced Chipset Features - MSI MS-6380 User Manual

Chapter 3

Advanced Chipset Features

Note: Change these settings only if you are familiar with the chipset.
Configure SDRAM Timing by
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to SPD enables CAS#
Latency, Row Precharge Time, RAS Pulse Width, RAS to CAS Delay and
Bank Interleave automatically to be determined by BIOS based on the
configurations on the SPD. Selecting User allows user to configure these
fields manually.
SDRAM Frequency
Use this item to configure the clock frequency of the installed SDRAM.
Settings are:
HCLK
HCLK+33
HCLK-33
The DRAM clock will be equal to the Host Clock.
The DRAM clock will be equal to the Host Clock plus
33MHz. For example, if the Host Clock is 100MHz, the
DRAM clock will be 133MHz.
The DRAM clock will be equal to the Host Clock minus
33MHz. For example, if the Host Clock is 133MHz, the
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