Passive Mode Pixel Clock And Data Pin Timing; Active Mode Timing - Intel PXA255 Developer's Manual

LCD Controller
Figure 7-14. Passive Mode Pixel Clock and Data Pin Timing
L_FCLK
L_LCLK
L_PCLK
LDD[3:0]
Figure 7-15. Active Mode Timing
L_FCLK
(VSYNC)
L_LCLK
(HSYNC)
L_BIAS
(OE)
L_PCLK
LDD[15:0]
7-16
Pixels 0 .. 3 Pixels 4 .. 7
PCP - Pixel Clock Polarity
0 - Pixels sampled from data pins on rising edge of clock
1 - Pixels sampled from data pins on falling edge of clock
For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical.
ENB set to 1
VSW = 0 VSW = 0
VSP = 0
HSW = 1 HSW = 1
HSP = 0
PCP = 0
ENB - LCD Enable
0 - LCD is disabled
1 - LCD is enabled
VSP - Vertical Sync Polarity
0 - Vertical sync clock is active high, inactive low
1 - Vertical sync clock is active low, inactive high
For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical.
VSW = Vertical Sync Pulse Width - 1
HSW = Horizontal Sync Pulse Width - 1
BFW = Beginning-of-Frame Horizontal Sync Clock Wait Count
BLW = Beginning-of-Line Pixel Clock Wait Count - 1
ELW = End-of-Line Pixel Clock Wait Count - 1
PPL = Pixels Per Line - 1
PCP = 0
Pixels 8 .. 11
BFW = 1 BFW = 1
BLW = 0 BLW = 0
PPL = 7 PPL = 7
Line 0 Data
HSP - Horizontal Sync Polarity
0 - Horizontal sync clock is active high, inactive low
1 - Horizontal sync clock is active low, inactive high
PCP - Pixel Clock Polarity
0 - Pixels sampled from data pins on rising edge of clock
1 - Pixels sampled from data pins on falling edge of clock
Intel® PXA255 Processor Developer's Manual
Pixels 12 .. 15 Pixels 16 .. 19
ELW = 0 ELW = 0
Line 1 Data Line 2 Data