Power Manager Registers; Power And Clock Supply Sources And States During Power Modes - Intel PXA255 Developer's Manual

Intel computer hardware user manual
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Clocks and Power Manager
Table 3-6. Power and Clock Supply Sources and States During Power Modes
Module
CPU,
Caches,
Buffers
Memory
Controller
LCD
Controller
DMA
Controller
General
Periphs.
OS timer
Interrupts
Real Time
Clock
Power
Manager
GP[3:0], PM
pads, Osc
pads
General IO
KEY:
T: Turbo clock
R: Run clock
V: Module powered off VCC.
I: Module powered off internal regulator
H: Module powered off VCCQ or VCCN
D: Module is dynamic or actively clocked
S: Module is static or clocks are gated.
3.5

Power Manager Registers

This section describes the 32-bit registers that control the Power Manager.
3-22
Supply Source
Turbo
Pw
Ck
Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck
Run/
Turbo
T
(R/T)
Mem
VCC
On
On
PLL
3.686
MHz Osc
VCC/
32.768
Reg
V
On
kHz Osc
(V/R)
HV/
Dynamic/
Batt
Static
H
D
(H/B)
(D/S)
H
Power Mode
Freq
Run
Idle
Change
R
Off
On
On
On
On
On
On
V
On
V
On
V
On
H
D
H
D
H
D
Intel® PXA255 Processor Developer's Manual
Sleep
Off Off
I
On
H
S

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