Intel PXA255 Developer's Manual page 55

Table 2-8. System Architecture Register Address Summary (Sheet 5 of 12)
Unit Address
I2S 0x4040_0000
0x4040_0000
0x4040_0004
0x4040_0008
0x4040_000C
0x4040_0010
0x4040_0014
0x4040_0018
0x4040_001C
through
0x4040_005C
0x4040_0060
0x4040_0064
through
0x4040_007C
0x4040_0080
AC97 0x4050_0000
0x4050_0000
0x4050_0004
0x4050_0008
0x4050_000C
0x4050_0010
0x4050_0014
0x4050_0018
0x4050_001C
0x4050_0020
0x4050_0024
through
0x4050_003C
0x4050_0040
0x4050_0044
through
0x4050_005C
0x4050_0060
0x4050_0064
through
0x4050_00FC
0x4050_0100
0x4050_0104
0x4050_0108
0x4050_010C
0x4050_0110
Intel® PXA255 Processor Developer's Manual
Register Symbol
SACR0 Global Control Register
SACR1 Serial Audio I
— Reserved
SASR0 Serial Audio I
— Reserved
SAIMR Serial Audio Interrupt Mask Register
SAICR Serial Audio Interrupt Clear Register
— Reserved
SADIV Audio Clock Divider Register.
— Reserved
SADR Serial Audio Data Register (TX and RX FIFO access Register).
POCR PCM Out Control Register
PICR PCM In Control Register
MCCR Mic In Control Register
GCR Global Control Register
POSR PCM Out Status Register
PISR PCM In Status Register
MCSR Mic In Status Register
GSR Global Status Register
CAR CODEC Access Register
— Reserved
PCDR PCM FIFO Data Register
— Reserved
MCDR Mic-in FIFO Data Register
— Reserved
MOCR Modem Out Control Register
— Reserved
MICR Modem In Control Register
— Reserved
MOSR Modem Out Status Register
System Architecture
Register Description
2
S/MSB-Justified Control Register
2
S/MSB-Justified Interface and FIFO Status Register
2-25