Intel PXA255 Developer's Manual page 192

Memory Controller
Table 6-2. MDCNFG Bit Definitions (Sheet 2 of 3)
0x4800_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0 0
Bits Name
9:8 DTC0[1:0]
10 DADDR0
11 DLATCH0
12 DSA1111_0
15:13
16
17
18 DWID2
6-10
DTC2
0 0 0 0 0 0 0
Timing Category for SDRAM pair 0/1.
00 - tRP = 2 clks, CL = 2, tRCD = 1 clks, tRAS(min) = 3 clks, tRC = 4 clks
01 - tRP = 2 clks, CL = 2, tRCD = 2 clks, tRAS(min) = 5 clks, tRC = 8 clks
10 - tRP = 3 clks, CL = 3, tRCD = 3 clks, tRAS(min) =7 clks, tRC=10 clks
11 - tRP = 3 clks, CL = 3, tRCD = 3 clks, tRAS(min) = 7 clks, tRC = 11 clks
tWR (write recovery time) is fixed at 2 clocks.
Used to configure the SDRAM timings to the SDRAM manufacturer's specifications. Clocks
referred to in the timings above are the number of SDCLKs. SDCLKs may not be
equivalent to memory clocks based on the MDREFRx[KxDB2].
See Figure 6-5 for a description of these timing numbers.
reserved
For an explanation on how the alternate addressing works, see
Return Data from SDRAM latching scheme for pair 0/1
0 – Latch return data using fixed delay from MEMCLK
1 – Latch return data with return clock
This bit must always be written with a '1' to enable using the return clock SDCLK for
latching data. For more detail on this return data latching, see
Use SA1111 Addressing Muxing Mode for pair 0/1. Setting this bit will override the
addressing bit programmed in MDCNFG:DADDR0.
For an explanation on how the SA1111 addressing works, see
— reserved
SDRAM enable for partition 2
For each SDRAM partition, there is an enable bit. A single (non-burst) 32-bit (or 16-bit if
MDCNFG:DWID2='1') access (read or write) to a disabled SDRAM partition triggers a CBR
DE2 refresh cycle to all partitions. When all partitions are disabled, the refresh counter is
disabled.
0 – SDRAM partition disabled
1 – SDRAM partition enabled
SDRAM enable for partition 3
For each SDRAM partition, there is an enable bit. A single (non-burst) 32-bit (or 16-bit if
MDCNFG:DWID2='1') access (read or write) to a disabled SDRAM partition triggers a CBR
DE3 refresh cycle to all partitions. When all partitions are disabled, the refresh counter is
disabled.
0 – SDRAM partition disabled
1 – SDRAM partition enabled
SDRAM data bus width for partition pair 2/3
0 – 32 bits
1 – 16 bits
MDCNFG
reserved
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
Memory Controller
8 7 6 5 4 3
DTC0
0 0 0 0 0 0 0 0
Figure 6-4
Section 6.5.4
Table 6-8.
2 1 0
0 0 0