Intel ® 5000P And 5000X Memory Controller Hubs (Mch); System Bus Interface; Processor Support - Intel S5000XAL Technical Product Specification

Intel server board technical product specification
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®
Intel
Server Board S5000PAL / S5000XAL TPS
®
3.1
Intel
5000P and 5000X Memory Controller Hubs (MCH)
This section will describe the general functionality of the memory controller hub as it is implemented on
this server board. Depending on the version of the server board in use, it may support either the Intel
®
5000P MCH or the Intel
The Memory Controller Hub (MCH) is a single 1432 pin FCBGA package which includes the following
core platform functions:
System Bus Interface for the processor sub-system
Memory Controller
PCI Express* Ports including the Enterprise South Bridge Interface (ESI)
FBD Thermal Management
SMBUS Interface
Additional information about MCH functionality can be obtained from the Intel
Server Board Family Datasheet, the Intel
(Yellow Cover), or the Intel
Note: Yellow Cover documents can only be obtained under NDA with Intel and ordered through an Intel
representative.
3.1.1
The MCH is configured for symmetric multi-processing across two independent front side bus interfaces
that connect to the Dual-Core Intel
uses a 64-bit wide 1066 or 1333 MHz data bus. The 1333 MHz data bus is capable of transferring data at
up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of
memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one
processor on each bus.
3.1.2
The server board supports one or two Dual-Core Intel
bus speeds of 667 MHz, 1066 MHz, and1333 MHz, and core frequencies starting at 2.67 GHz. Previous
®
generations of the Intel
Xeon
Note: Only Dual-Core Intel
MHz, 1066 MHz, and1333 MHz are supported on this server board. See the following table for a list of
supported processors.
Revision 1.4
5000X MCH. Features that are unique to a particular MCH will be so referenced.
®
5000P Memory Controller Hub External Design Specification
®
5000X Memory Controller Hub External Design Specification (Yellow Cover).

System Bus Interface

®
®
Xeon
processors 5000 sequence. Each front side bus on the MCH

Processor Support

®
processor are not supported on this server board.
®
®
Xeon
processors 5000 sequence, that support system bus speeds of 667
Intel order number: D31979-007
®
S5000 Series Chipsets
®
®
Xeon
processors 5000 sequence, with system
Functional Architecture
®
25

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