Intel 5000V Memory Controller Hub (Mch); System Bus Interface; Processor Support - Intel S5000VCL Technical Product Specification

Functional Architecture
3.1 Intel 5000V Memory Controller Hub (MCH)
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The memory controller hub (MCH) is a single 1432 pin FCBGA package that includes these
core platform functions:
System bus interface for the processor sub-system
Memory controller
PCI Express* ports including the enterprise south bridge interface (ESI)
FBD thermal management
SMBUS interface
3.1.1

System Bus Interface

The MCH is configured for symmetric multi-processing across two independent front side bus
interfaces that connect to the processors. Each front side bus on the MCH uses a 64-bit wide
1066- or 1333-MHz data bus. The 1333-MHz data bus can transfer data at up to 10.66 GB/s.
The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of memory.
The MCH is the priority agent for both front side bus interfaces, and is optimized for one
processor on each bus.
3.1.2

Processor Support

The server board supports one or two Dual-Core Intel
voltage Quad-Core Intel
and 1333 MHz, and core frequencies starting at 1.6 GHz. Previous generations of the Intel
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Xeon processor are not supported.
For a complete list of supported processors, see the following link:
http://support.intel.com/support/motherboards/server/S5000VCL
Note: Only Dual-Core Intel
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Xeon processor 5300 series, that support system bus speeds of 1066 MHz, and 1333 MHz are
supported.
8
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Xeon processor 5300 series, with system bus speeds of 1066 MHz,
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Xeon processors 5100 series or low-voltage Quad-Core Intel
Intel order number: D64569-007
Intel Server Board S5000VCL TPS
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Xeon processors 5100 series or low
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Revision 2.3