Chipset Features Setup - SOYO SY-K7AIA User Manual

BIOS Setup Utility

3-4.1 CHIPSET FEATURES SETUP

CHIPSET
FEATURES
System BIOS
Cacheable
Video BIOS
Cacheable
Memory Hole
At 15M-16M
AGP Aperture
Size (MB)
AGP ISA
Aliasing
K7 CLK_CTL
Select
SDRAM ECC
Setting
SDRAM
Timing setting
by
Setting Description
Disabled
Enabled The ROM area F0000H-FFFFFH is
cacheable.
Disabled
Enabled The video BIOS C0000H-C7FFFH is
cacheable.
Disabled
Enabled Some interface cards will map their
ROM address to this area. If this
occurs, select [Enabled] in this field.
128 This option specifies the following
AGP aperture sizes.
32,64,12
8,256
Disabled Set this item to enabled for better
compatibility with ISA VGA.
Enabled
Optimal The Clock Control register (Clk_Ctl)
specifies how the processor will ramp
Default
up the processor clock during low
power modes
Disabled When this option is enabled, the
SDRAM is configured to support
Enabled
single-bit correction/double-bit
detection codes (ECC) for checking
the integrity of transactions with
system memory.
Auto If this item is set to manual, the items
concerning memory performance and
speed are released for change by the
user. Only experienced users should
Manual
change these items. If set to auto, the
memory items will be set
automatically.
61
SY-K7AIA
Note
Default
Default
Default
Default
Default
Default