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Motherboard Description
Memory write FIFO (MWF)
Memory read FIFO (MRF)
PCI/APCI (AGP-PJCI) write buffer
PCI/APCI read buffer
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Transaction Queues:
Command queue (CQ)
Memory write queue (MWQ)
Memory read queue (MRQ)
Probe (snoop) queue (PQ)
1-9.2 Integrated memory controller
The integrated memory controller has the following features:
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Memory Request Organizer (MRO) – Serves as a data crossbar,
determines request dependencies, and optimizes scheduling of
memory requests.
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The AMD-751 system controller supports the following
concurrences:
Processor-to-main-memory with PCI-to-Main-memory
Processor-to-main-memory with AGP-to-Main-memory
Processor-to-=PCI with PCI-to-Main-memory or AGP-to-main-
memory
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Memory error correcting code (ECC) support
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Supports the following DRAM:
Up to three non-buffered PC-100 SDRAM DIMMs using 16-
Mbit, 64Mbit-, and 128Mbit technology
64-bit data width, plus 8-bit ECC paths
Flexible row and column addressing
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Supports up to 768 Mbytes of memory
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Four open pages within one CS (device selected by chip select) for
one quadword
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Default two-page leapfrog policy for eight quadword requests
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BIOS-configurable memory-timing parameters and configuration
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SY-K7AIA
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