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Motherboard Description
parameters
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3.3-V memory interface operation with no external buffers
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Four cache lines (32 quadwords) of processor-to-DRAM posted write
buffers with full read-around capability
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Concurrent DRAM write back and read-around-write
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Burst read and write transactions
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Decoupled and burst DRAM refresh with staggered CS timing
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Provides the following refresh options:
Programmable refresh rate
CAS-before-RAS
Populated banks only
Chipset powerdown via SDRAM automatic refresh command
Automatic refresh of idle slots – improves bus availability for
memory access by the processor or system
1-9.3 PCI Bus Controller
The PCI bus controller has the following features:
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Compliance with PCI Local Bus Specification, Revision 2.2
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Supports six PCI masters
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32-bit interface, compatible with 3.3-V and 5-V PCI I/O
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Synchronous PCI bus operation up to 33 MHz
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PCI-initiator peer concurrence
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Automatic processor-to-PCI burst cycle detection
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Four-entry, 64-bit PCI master (processor or AGP) write FIFO
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Extensive utilization of FIFOs
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Zero wait-state PCI initiator and target burst transfers
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PCI-to-DRAM data streaming up to 132 Mbytes per second
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Enhanced PCI command optimization, such as memory read line
(MRL), memory read multiple (MRM), and memory-write-and-
invalidate (MWI)
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Timer-enforced fair arbitration between PCI initiators
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Supports advanced concurrency
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Supports retry disconnect for improved bus utilization
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SY-K7AIA
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