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Motherboard Description
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PCI read buffer keeps track of each master
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PCI target request queue
1-9.4 AGP Features
The AGP features include the following:
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Bus Features
Compliance with AGP 2.0 specification
Synchronous 66-MHz 1x and 2x data-transfer modes
Multiplexed and demultiplexed transfers
Up to four pipelined grants
Support of side band address (BA) bus
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Request Queue Features
Separate read-request and write-request queues
Reordering of high-priority requests over low-priority requests
in queue
Simultaneous issuing of requests form both the write queue and
read 2queue
Selects next request to optimize bus utilization
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Transaction Queues
Memory-to-AGP and processor-to-AGP transaction queues
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FIFO Features
16-entry (64-bit) AGP-to-memory write FIFO
64-entry (64-bit) memory-to9-AGP read FIFO
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Secondary PCI Bus Features
Pipelined burst reads and writes
Extensive utilization of FIFOs
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GART (graphics address remapping table) Features
Conventional (two-level) GART scheme
Eight-entry, fully-associative GART table cache (GTC)
Three fully-associative GART directory caches (GDC)
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One 4-entry for PCI
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One 8-entry for the processor
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One 16-entry for AGP
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SY-K7AIA
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