4) Signal Level
LOW : 0 V to +0.8V
HIGH : +2.4 V to 5.0 V
5) Specifications
6) Timing Charts
a) Data receiving timing
Item
Mode
Data bit length
Input prime
Receive buffer
Control
b) On-line --> off-line switching timing by ON-LINE SW
c) Off-line --> on-line switching timing by ON-LINE SW
d) INPUT PRIME timing (when set to the effective INPUT PRIME signal)
Description
Compatibility mode, Nibble mode, ECP mode
8 bits (in the compatibility mode)
Valid/Invalid
8K, 20K, 50K, 100K, 1M Bytes
Handshaking control is performed in each mode. Data received from the host is stored in the
receive buffer. Busy control is performed. Signal lead control is performed.