System Backplane; I/O Subsystem - HP RP7405/7410 User Manual

Introduction
hp rp7405/rp7410 Overview

System Backplane

The system backplane comprises the system clock generation logic, the system reset generation logic,
DC-to-DC converters, power monitor logic, and two Local Bus adaptor (LBA) link-to-PCI converter ASICs. It
also includes connectors for attaching the cell boards, PCI backplane, MP Core I/O MP/SCSI boards, SCSI
cables, bulk power, chassis fans, front panel display, intrusion switches, and the system scan card. Unlike
Superdome or the rp8400, there are no XBC chips on the system backplane. The "crossbar-less" back-to-back
CC connection increases performance and reduces costs.
There are only two sets of cell board connectors, because the server has only two cells
Also, only half of the MP Core I/O board set connects to the system backplane. The MP/SCSI boards plug into
the backplane, while the LAN/SCSI boards plug into the PCI Backplane.

I/O Subsystem

All of the I/O is integrated into the system by way of the PCI busses. The CC on each cell board communicates
with one SBA over the SBA link. The SBA link consists of both an inbound and an outbound link with an
effective bandwidth of approximately 1 GB/sec. The SBA converts the SBA link protocol into "ropes". SBA can
support up to 16 of these high-speed bi-directional links for a total aggregate bandwidth of approximately 4
GB/sec. The LBA acts as a bus bridge, supporting either one or two ropes, and capable of driving either
PCI-2x Turbo (33 MHz x 64 bits) or PCI-4 Twin Turbo (66 MHz x 64 bits) respectively.
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Chapter 1