AOpen MX3W-V User Manual page 58

Advanced Chipset Features ? SDRAM RAS Precharge Time
SDRAM RAS The RAS Precharge means the timing to inactive
Precharge Time RAS and the timing for DRAM to do precharge
before next RAS can be issued. RAS is the address
3
latch control signal of DRAM row address. The
2
default setting is 3 clocks.
Advanced Chipset Features ? Video BIOS Cacheable
Video BIOS Allows the video BIOS to be cached to allow faster
Cacheable video performance.
Enabled
Disabled
Advanced Chipset Features ? Video RAM Cacheable
Video RAM This item lets you cache Video RAM A000 and
Cacheable B000.
Enabled
Disabled
Advanced Chipset Features ? Memory Hole At 15M-16M
Memory Hole At This option lets you reserve system memory area
15M-16M for special ISA cards.
code/data of these areas from the ISA bus directly.
Enabled
Normally, these areas are reserved for memory
Disabled
mapped I/O card.
Advanced Chipset Features ? Delayed Transaction
Delayed Transaction
This item lets you control the Delayed Transaction
function of the PIIX4 chipset (Intel PCI to ISA
Enabled
bridge). This function is used to meet latency of PCI
Disabled
cycles to or from ISA bus. Try to enable or disable
it, if you have ISA card compatibility problem.
Advanced Chipset Features ? On-Chip Video
AWARD BIOS
The chipset accesses
3-11