AOpen MX3W-V User Manual page 47

The following table lists the recommended DRAM combinations of DIMM:
DIMM Bit size Single/
Data chip per side Double side
1M by 16 1Mx64 x1
1M by 16 1Mx64 x2
2M by 8 2Mx64 x1
2M by 8 2Mx64 x2
4M by 16 4Mx64 x1
4M by 16 4Mx64 x2
4M by 32 4Mx64 x1
4M by 32 4Mx64 x2
8M by 8 8Mx64 x1
8M by 8 8Mx64 x2
8M by 16 8Mx64 x1
8M by 16 8Mx64 x2
8M by 32 8Mx64 x1
8M by 32 8Mx64 x2
16M by 8 16Mx64 x1
16M by 8 16Mx64 x2
The following table lists the possible DRAM combinations that is NOT
recommended:
DIMM Bit size per Single/
Data chip side Double side
4M by 4 4Mx64 x2
16M by 4 16Mx64 x1
16M by 4 16Mx64 x2
Tip: The parity mode uses 1 parity bit for each byte, normally
it is even parity mode, that is, each time the memory data is
updated, parity bit will be adjusted to have even count "1" for
each byte. When next time, if memory is read with odd
number of "1", the parity error is occurred and this is called
single bit error detection.
AWARD BIOS
Chip DIMM size Recommended
count
4 8MB Yes
8 16MB Yes
8 16MB Yes
16 32MB Yes
4 32MB Yes
8 64MB Yes
2 32MB Yes
4 64MB Yes
8 64MB Yes
16 128MB Yes
4 64MB Yes
8 128MB Yes
2 64MB Yes
4 128MB Yes
8 128MB Yes
16 256MB Yes
Chip DIMM Recommended
count size
32 64MB No
16 128MB No
32 256MB No
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