AOpen AX3L User Manual page 46

Chipset Features
DRAM ECC
Function
Enabled
Disabled
Chipset Features
CPU-to-PCI IDE
Posting
Enabled
Disabled
Chipset Features
Video BIOS
Cacheable
Enabled
Disabled
Chipset Features
Video RAM
Cacheable
Enabled
Disabled
DRAM ECC Function
This item lets you enable or disable DRAM ECC
function. The ECC algorithm has the ability to detect
double bit error and automatically correct single bit
error.
CPU-to-PCI IDE Posting
To enable or disable CPU to PCI IDE post write
cycle. The IDE write cycles will be queued in the
FIFO or buffer, and CPU can be released to do next
job. Disable it, if you find any IDE compatibility
problem.
Video BIOS Cacheable
Allows the video BIOS to be cached to allow faster
video performance.
Video RAM Cacheable
This item lets you cache Video RAM A000 and B000.
AWARD BIOS
3-13