AOpen AX3L User Manual page 45

AWARD BIOS
Chipset Features
EDO DRAM Read
Burst
x333
x222
Chipset Features
EDO DRAM Write
Burst
x333
x222
Chipset Features
SDRAM(CAS
Lat/RAS-to-CAS)
2/2
3/3
Chipset Features
SDRAM RAS
Prechatge Time
2T
3T
3-12
EDO DRAM Read Burst
Read Burst means to read four continuous memory
cycles on four predefined addresses from the DRAM.
The default value is x222 for 60ns EDO DRAM.
Which means the 2nd,3rd and 4th memory cycles
are 2 CPU clocks for EDO. The value of x is the
timing of first memory cycle.
EDO DRAM Write Burst
Write Burst means to write four continuous memory
cycles on four predefined addresses to the DRAM.
The default value is x222 for 60ns EDO DRAM.
Which means the 2nd,3rd and 4th memory cycles
are 2 CPU clocks for EDO. The value of x is the
timing of first memory cycle.
SDRAM(CAS Lat/RAS-to-CAS)
These are timing of SDRAM CAS Latency and RAS
to CAS Delay, calculated by clocks. They are
important parameters affects SDRAM performance,
default is 2 clocks. If your SDRAM has unstable
problem, change 2/2 to 3/3.
SDRAM RAS Precharge Time
The RAS Precharge means the timing to inactive
RAS and the timing for DRAM to do precharge before
next RAS can be issued. RAS is the address latch
control signal of DRAM row address. The default
setting is 3 clocks.