Agilent Technologies Infiniium 90000 A Service Manual page 141

Chapter 7: Theory of Operation
Block-Level Theory
Power Supply Assembly
The AC input to the power supply is 100–240 VAC ±10%. Maximum input power is 800 W. The
AC input frequency is 47 to 63 Hz.
Filtered voltages of +3.3 V, +2.5 V, +1.8 V, +1.2 V, -6 V, -5.2 V, -5 V, and –2.3 V are supplied and
distributed throughout the oscilloscope.
Monitor Assembly
The Flat Panel Display (FPD) monitor is a thin film liquid-crystal display (TFT-LCD). This FPD
is an 12.1 inch diagonal, 1024 by 768 pixel XGA color monitor.
Acquisition System
There are two acquisition assemblies. The upper acquisition assembly circuitry samples,
digitizes, and stores the signals for channels 3 and 4 while the lower acquisition assembly does
the same for channels 1 and 2. The acquisition boards contain the TUT modules, the Onboard
ADC, the clock distribution, the data management ASICs, the external acquisition memory, the
Merlin ADCs, the communication and programming FPGA, and the supporting power supply
circuitry. The block diagram for the acquisition boards can be seen in Figure 7-6.
Backplane Assembly
The backplane board is essentially a device on the PCI-Express bus connected by two SATA
cables to the motherboard. The backplane board recieves +12V power through a distribution
board from the supply and all voltage are dervied from switches and other circuitry. Most of these
are on the backplane board, with some further distribution and generation done on the
acquisition boards. Refer to Figure 7-3 for the block diagram of the backplane assembly.
The backplane board uses three identical buses to communicate with three different downstream
FPGAs. One is used to control the trigger functions on the backplane board and one is on each
of the two acquisition boards. The acquisition board FPGAs are used to program the parts on
the acquisition boards. On power-up, after the software recognizes the acquisition boards, the
driver loads the trigger FPGA and the acquisition FPGAs using an 8-bit parallel bus with
miscellaneous control signals. There is a separate bus for each FPGA so timing problems and
reflections could be minimized. After programming is complete, the downstream FPGAs each
communicate with the BFPGA using their 8-bit data bus along with a 62.5 MHz communication
clock, a 2-bit command bus, a ready signal to the BFPGA, a Data_valid signal from the BFPGA,
and an Interrupt line,
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